FIG. 4 is a block diagram illustrating a conventional PLL frequency synthesizer. In FIG. 4, the frequency synthesizer comprises a voltage-controlled oscillator 1 (referred to as VCO hereinafter) with an oscillation frequency of f.sub.1 ; a frequency divider 2 with a frequency dividing ratio of N1; a reference oscillator 3 with a frequency of f.sub.2 ; a frequency divider 4 with a frequency dividing ratio of N2; a phase comparator 5; and a low-pass filter 6 (referred to as LPF hereinafter).
In this configuration, signal S.sub.1 at a frequency of f.sub.1 output from VCO 1 is subject to processing of frequency dividing (1/N1) by frequency divider 2, and signal S.sub.2 formed is input to phase comparator 5.
On the other hand, signal S.sub.3 at a frequency of f.sub.2 output from reference oscillator 3 is subject to processing of frequency dividing (1/N2) by frequency divider 4, and signal S.sub.4 formed is input to phase comparator 5.
At phase comparator 5, phase comparison with signal S.sub.2 with reference to input signal S.sub.4 is performed. The output of phase comparator 5 is made of an AC component and a DC component (the error output current), and it is output to LPF 6.
For the DC component in phase comparator 5, the polarity (positive/negative) and the magnitude vary depending on whether the phase of signal S.sub.2 leads or lags signal S.sub.4.
In LPF 6, the AC component is removed from the output of phase comparator 5, and only the DC component is extracted and fed back to VCO 1.
In this way, the center frequency of output signal S.sub.1 of VCO 1 always follows the phase of output signal S.sub.3 of reference oscillator 3, and, with the following relationship, VCO 1 oscillates at frequency f.sub.2 in the so-called locked state. EQU f.sub.1 /N1=f.sub.2 /N2.
Also, the value of f.sub.2 can be changed at will in steps of (f.sub.2 /N2) by changing frequency dividing ratio N1 of frequency divider 2.
However, in the aforementioned circuit, immediately after the power source is turned on and the circuit is established, and when frequency dividing ratio N1 of frequency divider 2 is changed, the system exits from the locked state (enters the unlocked state), and only the DC component from LPF 6 is fed back to VCO 1. After a little while, VCO 1 reenters the locked state.
The time needed for transition from the unlocked state to the locked state (the lockup time) depends on capacitor C.sub.1 (such as 500 pF), capacitor C.sub.2 (such as 0.2 .mu.F), and resistor R.sub.1 (such as 10 .OMEGA.) that form LPF 6. For the aforementioned circuit, it is difficult to shorten the lockup time because of the need for maintaining a stable locked state.
In particular, the time needed for charging capacitor C.sub.2, which has a large capacitance, is also a factor.
It is an object of this invention to provide a frequency adjusting circuit in which the lockup time of the voltage-controlled oscillator component can be shortened.